Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming of charge storage or trapping layers or other physical phenomena, determine the data value of each cell. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, cellular telephones and removable memory modules.
Flash memory typically utilizes one of two basic architectures known as NOR flash and NAND flash. The designation is derived from the logic used to read the devices. In NOR flash architecture, a column of memory cells are coupled in parallel with each memory cell coupled to a bit line. In NAND flash architecture, a column of memory cells are coupled in series with only the first memory cell of the column coupled to a bit line.
As the performance of electronic systems employing flash memory devices increases, flash memory device performance should also increase. A performance increase includes reducing power consumption, increasing speed, and increasing the memory density. One way to accomplish these tasks is by decreasing the size of the memory array and its individual devices.
Unfortunately, there can be resulting problems with decreasing device sizes. For example, as the channel length and gate oxide thickness are reduced in a field-effect transistor, leakage current generally increases. One type of leakage current is gate induced drain leakage (GIDL) that results from the depletion at the drain surface below the gate-drain overlap region.
GIDL can cause a problem referred to as program disturb during a programming operation of a flash memory array. For example, FIG. 1 illustrates a portion of a typical prior art NAND flash memory array. During a program operation to program a memory cell 101, the word line 102 coupled to that cell 101 may be biased with a 20V programming pulse. The bit line 104 coupled to that cell may be brought to ground potential. This provides a gate to source potential of 20V across the cell 101 to be programmed.
The other cells on the selected word line 102 will also have the 20V programming pulse applied. In order to inhibit these cells from being programmed, their bit lines 104 may be biased to Vcc. Additionally, the remaining unselected word lines may be biased with 10V pulses. This biasing creates a channel voltage of approximately 7V on the unselected cell 103. This provides a gate to source voltage of approximately 13V that is generally below the required programming voltage for such cells.
However, the resulting drain to gate field for the drain select gates (SGD) and source select gates (SGS) may, in this scenario, approach 7V, which can cause the 7V channel potential on the unselected cell 103 to leak away, thus creating the possibility that the unselected cell 103 is programmed. This is referred to in the art as program disturb. To mitigate the effects of GIDL, and thus to mitigate the occurrence of program disturb, select transistors of the NAND strings are generally sized to have a gate length much greater than any of the memory cells of the string. Increasing the gate length of the select transistors runs counter to the desire to decrease memory array size.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative memory device architectures.